Verilog Module Testbench Generator

Verilog Module Testbench Generator

Generate clean, executable Verilog testbench boilerplate (`*_tb.v`) for functional simulation of your module.

VERILOG TESTBENCH

Module: _tb.v

Target Module Name
Module Name
Total Inputs (Custom)
0
Total Outputs (Custom)
0

Generated Verilog Code

// Configure module inputs in the "Module Configuration" tab and click "Generate Testbench".

Module I/O Definition

Module Identification

Inputs (stimulus signals)

Format: `Name: [Width]`. Clock (CLK) and Reset (RESET) are added automatically.

Outputs (response signals)

Format: `Name: [Width]`. Leave width empty for 1-bit signals (default wire/reg).

Testbench Settings

Scroll to Top