SystemVerilog Assertion Property Specification File SystemVerilog Assertion Generator SVA Architect SystemVerilog Assertion Generator Assertion Name Global Signals Active Low (!rst_n) Active High (rst) Trigger (Antecedent) Trigger Logic Is High (Level) Rose ($rose) Fell ($fell) Implication Operator |-> (Overlapping) |=> (Non-Overlapping) Check (Consequent) Delay (Cycles) Type Fixed (##n) Range (##[n:m]) Severity Error ($error) Fatal ($fatal) Warning ($warning) Timing Visualization Generated SystemVerilog Code
